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AS1112
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 12. Dot Correction Data Input Timing Diagram
MODE
V CC
GND
Dot Correction Mode
Data Input Cycle n
Dot Correction Mode
Data Input Cycle n +1
SDI
DC n -1
LSB
DC n
MSB
DC n
MSB-1
DC n
MSB-2
DC n
LSB+1
DC n
LSB
DC n +1
MSB
DC n +1
MSB-1
t SU0
t WH0
CLK
1
2
1
95
96
1
2
t WL0
SDO
DC n -1
MSB
DC n -1
MSB-1
DC n -1
MSB-2
DC n -1
LSB+1
DC n -1
LSB
DC n
MSB
DC n
MSB-1
DC n
MSB-2
t WH2
t SU1
t H1
LD
Setting Greyscale Brightness
The brightness of each channel output can be adjusted using a 12 bits-per-channel PWM control scheme which results in 4096 brightness steps,
from 0% to 100% brightness. The brightness level for each output is calculated as:
%Brightness =
GS n
4095
x 100
(EQ 4)
Where:
GS n is the programmed greyscale value for OUT n (GS n = 0 to 4095);
n = 0 to 15 greyscale data for all outputs.
The device powers up with the following default seetings: GS = 4095 and DC = 63.
The input shift register shifts greyscale data into the greyscale register for all channels simultaneously. The complete greyscale data format con-
Note: The data packet must be clocked in with the MSB first.
Figure 13. Greyscale Data Packet Format
MSB
LSB
191
180
179
12
11
0
GS15.11
...
GS15.0
GS14.11
...
GS1.0
GS0.11
...
GS0.0
GS OUT15
GS OUT14:GS OUT1
GS OUT0
When pin MODE is tied to GND, the AS1112 enters greyscale data input mode. The device switches the input shift register to 192-bit width. After
all data is clocked in, the rising edge of the LD signal latches the data into the greyscale register (see Figure 14) .
All greyscale data in the input shift register is replaced with status information data (SID) after latching into the greyscale register.
Revision 1.13
12 - 19
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